ENDIANON=0, SWAPON=0, FRQSEL=00, PHASE=00, DIRSEL=0, FORMAT=00
Output Control Block Output Interface Register
| PHASE | Data delay in serial RGB format (based on OUTCLK) 0 (00): 0 cycle 1 (01): 1 cycle 2 (10): 2 cycles 3 (11): 3 cycles |
| DIRSEL | Invalid data position control in serial RGB format 0 (0): Invalid data is output following valid (RGB) data. 1 (1): Invalid data is output prior to valid (RGB) data. |
| FRQSEL | Clock frequency division control 0 (00): No frequency division, parallel RGB 1 (01): Setting prohibited 2 (10): Quarter frequency (serial RGB) 3 (11): Setting prohibited |
| FORMAT | Output format select 0 (00): RGB888; select RGB888 as dither output format. 1 (01): RGB666; select RGB666 as dither output format. 2 (10): RGB565; select RGB565 as dither output format. 3 (11): Serial RGB; select RGB888 as dither output format. |
| SWAPON | Pixel order control 0 (0): In the order of RGB 1 (1): In the order of BGR |
| ENDIANON | Bit endian change control 0 (0): Descending order (little endian) 1 (1): Ascending order (big endian) |